With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and that have increased device density. To accomplish this, there is a pressing need to form devices with aggressive scaling of miniaturized device patterns of ever-smaller line widths.
With increased pressure on the design rules, including, for example, structure size and pitch of semiconductor devices, it has become increasingly difficult to form sufficiently fine pitch patterns due to the resolution limitations of conventional photolithography processes that are used to form the patterns. However, such finely dimensioned line and space patterns, known as “L/S patterns” are critical to device design and integration.
Among the various methods proposed to improve the resolution of conventional photolithography processes, one method, known as the self-aligned-reverse patterning method, or SARP method, has enjoyed widespread popularity. In this approach, a first photolithography pattern is applied to an underlying layer to be patterned. The first photolithography deposition applies structures that are at or near the size and pitch resolution limitations of the photolithography system. A spacer layer is deposited on the resulting structures. The spacer layer is anisotropically etched to form spacers at sidewalls of the structures. The resulting dimensions of the spacers can be accurately controlled by controlling the etch parameters. The original structures are removed, and the spacers remain as an etch mask that can be used to pattern the underlying layer, to result in structures that are finer in width and closer in pitch that that attainable by the photolithography system itself.
There are certain limitations, however, that limit the success of this approach. For example, in a case where certain high-density regions of a device are to include high-density patterns having relatively narrower width and tighter pitch, and low-density regions of a device are to include low-density patterns having relatively larger width and are more spaced apart in pitch, the low-density patterns and high-density patterns are patterned at different times, using different processes. For example, the low-density patterns can be patterned using conventional photolithography tooling, and the high-density patterns, on the same device, are patterned using the SARP approach. As a result, misalignment can occur between the low-density patterns and the high-density patterns, as they are patterned at different times. Also, since they are patterned at different times, extra photolithography steps are required, increasing manufacturing costs.